Introduction/Code Features/Target Platform/Parallelization Approach
VAMOS aims at producing an advanced VHDL simulator that benefits from the state of the art of parallel simulation techniques, computer architectures and software technologies. This represents a nontrivial problem due to the complexity of the VHDL language, the inherent difficulties in parallelizing a discrete event simulation and the optimization techniques that must be applied.
Therefore, the parallel simulator is being developed to run in coarse grained multiprocessors with shared memory .
In order to execute a VHDL description several intermediate steps are needed. First of all, the design files containing the VHDL source code must be analyzed to produce a design library that allows management and reusability of the design information. VAMOS project uses LVS, a commertial tool from LEDA, to provide this interface.
The executable model is generated by the VHDL elaborator, which transforms a design hierarchy into an heterarchy of VHDL processes interconnected by a network of VHDL signals, and their associated information. TGI provides a VHDL'87 elaborator as background information of FORMAT project.
In order to be executed the elaborated model must be translated to native code. For portability reasons, this is done by generating a set of C files that are then linked with design-independent libraries and compiled to obtain the parallel VHDL simulator.
Finally, the elaborated processes are concurrently executed by a VHDL simulator, called the VHDL kernel. Elaborated processes are composed by VHDL sequential statements, that are cyclically executed. When a process executes a wait statement suspends its execution flow until the conditions of the statement are satisfied and then, resumes its execution flow. Each elaborated process is sensitive to events on signals; in other words, its execution is event-driven. The VHDL kernel manages the time advance, the activity of the processes during the simulation, and the updating of the signals.
The simulator includes also built-in debugging functionality, mostly implemented in the debugger thread. The exception are traces of signals and variables, that are also parallelized.
The simulator uses the POSIX 1003.1c standard API for threads in order to be portable. The UPM has also implemented a thread library specially optimized for the VHDL simulator in the platform that is most spreaded in the market (SPARC multiprocessors with Solaris 2.x)