VHDL Advanced Multiprocessor Optimized Simulation

Introduction/Code Features/Target Platform/Parallelization Approach


One of the current problems in VLSI design is that simulation runs take excessive amounts of time to execute. Run-times of several days are not uncommon for complex designs in a process that is supposed to be interactive, causing increased design costs and longer time to market. The trend is for run-times to lengthen since the complexity of simulation is outstripping performance improvements in computers. The underlying cause of this problem is that most of the simulation tools commercially available perform sequential simulation of the design.

VAMOS aims at producing an advanced VHDL simulator that benefits from the state of the art of parallel simulation techniques, computer architectures and software technologies. This represents a nontrivial problem due to the complexity of the VHDL language, the inherent difficulties in parallelizing a discrete event simulation and the optimization techniques that must be applied.

Target Platform

Few potential users of a VHDL parallel simulator have a massive parallel computer. The most spreaded platforms are: With current local area networks it is very dubtious that a distributed VHDL simulator can achieve a reasonable performance in a workstation network, due to the high dependency between processes and the cost of communication.

Therefore, the parallel simulator is being developed to run in coarse grained multiprocessors with shared memory .

Code Features

VHDL is a Hardware Description Language adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE). Its flexibility allows to describe a design with very different levels of abstraction: from high-level behavioural designs to the RT or gate level. This favoures a top-down approach with succesive refinement steps.

In order to execute a VHDL description several intermediate steps are needed. First of all, the design files containing the VHDL source code must be analyzed to produce a design library that allows management and reusability of the design information. VAMOS project uses LVS, a commertial tool from LEDA, to provide this interface.

The executable model is generated by the VHDL elaborator, which transforms a design hierarchy into an heterarchy of VHDL processes interconnected by a network of VHDL signals, and their associated information. TGI provides a VHDL'87 elaborator as background information of FORMAT project.

In order to be executed the elaborated model must be translated to native code. For portability reasons, this is done by generating a set of C files that are then linked with design-independent libraries and compiled to obtain the parallel VHDL simulator.

Finally, the elaborated processes are concurrently executed by a VHDL simulator, called the VHDL kernel. Elaborated processes are composed by VHDL sequential statements, that are cyclically executed. When a process executes a wait statement suspends its execution flow until the conditions of the statement are satisfied and then, resumes its execution flow. Each elaborated process is sensitive to events on signals; in other words, its execution is event-driven. The VHDL kernel manages the time advance, the activity of the processes during the simulation, and the updating of the signals.

Parallelization Approach

The approach followed is parallel synchronous simulation, with each VHDL process implemented as a thread and the VHDL kernel splitted into several threads. Each simulation cycle is divided in two phases, separated by synchronization barriers. Input/output is decoupled from the simulation through an I/O monitor thread. Threads are dynamically allocated to processors to achieve good load balancing.

The simulator includes also built-in debugging functionality, mostly implemented in the debugger thread. The exception are traces of signals and variables, that are also parallelized.

The simulator uses the POSIX 1003.1c standard API for threads in order to be portable. The UPM has also implemented a thread library specially optimized for the VHDL simulator in the platform that is most spreaded in the market (SPARC multiprocessors with Solaris 2.x)

Last update July 22, 1996